What is the hardware that carries out instructions of a computer program called?

Central Process Unit

The computer's central processing unit (CPU) is the portion of a computer that retrieves and executes instructions. The CPU is essentially the brain of a CAD system. It consists of an arithmetic and logic unit (ALU), a control unit, and various registers. The CPU is often simply referred to as the processor. The ALU performs arithmetic operations, logic operations, and related operations, according to the program instructions.

The control unit controls all CPU operations, including ALU operations, the movement of data within the CPU, and the exchange of data and control signals across external interfaces (system bus). Registers are high-speed internal memory-storage units within the CPU. Some registers are user-visible; that is, available to the programmer via the machine instruction set. Other registers are dedicated strictly to the CPU for control purposes. An internal clock synchronizes all CPU components. The clock speed (number of clock pulses per second) is measured in megahertz (MHz) or millions of clock pulses per second. The clock speed essentially measures how fast an instruction the CPU processes.

CPU

The central processing unit runs everything. It fetches program instructions over its “instruction side” (IS) bus, reads data over its “data side” (DS) bus, executes the instructions, and writes the results over the DS bus. The CPU can be clocked by SYSCLK at up to 80 MHz, meaning it can execute one instruction every 12.5 ns. The CPU is capable of multiplying a 32-bit integer by a 16-bit integer in one cycle, or a 32-bit integer by a 32-bit integer in two cycles. There is no floating point unit (FPU), so floating point math is carried out by software algorithms, making floating point operations much slower than integer math.

The CPU is the MIPS32® M4K® microprocessor core, licensed from Imagination Technologies. The CPU operates at 1.8 V (provided by a voltage regulator internal to the PIC32, as it’s used on the NU32 board). The interrupt controller, discussed below, can notify the CPU about external events.

Internal CPU Buses

The CPU buses are the mechanisms that interconnect the CPU’s other components: the ALU, the CU, and registers (see Figure 4-22). Buses are simply wires that interconnect the various other components within the CPU. Each bus’s wire is typically divided into logical functions, such as data (which carries data, bidirectionally, between registers and the ALU), address (which carries the locations of the registers that contain the data to be transferred), control (which carries control signal information, such as timing and control signals, between the registers, the ALU, and the CU), etc.

Note: To avoid redundancy, buses will be discussed in more detail in Chapter 7.

Memory-Read/Write

The CPU always controls the direction of data flow on the DB because, although it is bidirectional, data can move in only one direction at a time. The CPU provides a special read/write control (R/W) signal (Fig. 3.2) that activates circuits in the memory, which determine the direction of the data flow. For example, when the read/write (R/W) line is high, the CPU transfers information from a memory location to the CPU.

The timing diagram for a memory-read operation is shown in Fig. 3.3.

Suppose the computer has been given the instruction to read data from memory location number 10. To perform the read operation, the CPU raises the R/W line to the high-level to activate memory circuitry in preparation for a read operation. Almost simultaneously, the address for location 10 is placed on the AB (“address valid” in Fig. 3.3). The number 10 in 16-bit binary (0000 0000 0000 1010) is sent to the memory in the AB. The binary electric signals corresponding to 10 operate the specific circuits in the memory to cause the binary data at that location to be placed on the DB. The CPU has an internal register that is activated during this read operation to receive and store the data. The data are then processed by the CPU during the next cycle of operation according to the relevant instruction.

A similar operation is performed whenever the CPU is to send data from one of its internal registers to memory, which is a “write” operation. In this case, the R/W line will be set at the logical level opposite to the read operation (i.e., low in this example). During the write operation, the data to be sent are placed on the DB at the same time the destination address is placed on the AB. This operation will transfer data from the CPU source location to the destination, which could be a memory location in RAM or could be an external device (as will be explained later).

1.3.1 System Operation

The CPU controls the system data transfers via the data and address buses and additional control lines. A clock circuit, usually containing a crystal oscillator (as found in digital watches), is required; this produces a precise fixed frequency signal that drives the microprocessor along. The CPU operations are triggered on the rising and falling edges of the clock signal, allowing their exact timing to be defined. This allows events in the CPU to be completed in the correct sequence, with sufficient time allowed for each step. The CPU generates all the main control signals based on the clock. A given CPU can be used in different system designs, depending on the type of application, the amount of memory needed, the I/O requirements and so on.

The address decoder controls access to memory and I/O registers for a particular design. Typically, a programmable logic device (PLD) is used to allocate each memory chip to a specific range of addresses. An input address code in a particular range generates a chip select output, which enables that device. The I/O port registers, which are set up to handle the data transfer in and out of the system, are also allocated particular addresses by the same mechanism, and accessed by the CPU in the same way as memory locations. The allocation of addresses to particular peripheral devices is called a memory map (Figure 1.6b).

Publisher Summary

The central processing unit (CPU) guides the computer through the various steps of solving a problem. Data enters the computer through an input unit, is processed by the central processing unit, and is then made available to the user through an output unit. A logical view of a computer shows what functions the computer performs. A physical view of a computer shows how the mechanisms of the computer actually perform these functions. The three logical units that make up the central processing unit are the arithmetic and logic unit (ALU), main storage, and the control unit. Main storage retains active programs and data. It is relatively expensive, so secondary storage is used to store programs and data until they are needed in main storage. The set of a computer's built-in operations is called its “instruction set.” A computer program is a set of instructions that tells a computer how to solve a particular problem. A computer program must be in main storage for a computer to be able to perform its instructions.

5.15.2.4.2.1 The processor unit

This central processing unit (CPU) of PLC, that is a microprocessor by design and functionality. The main function of this unit is to sense input values via its I/O modules, generate control signals following the input signals and the predefined instruction (stored in the memory unit as program). The processed decision is then transferred to the output devices attached to I/O modules to update the output variables [51]. A typical CPU process cycle has been given in Fig. 40 demonstrating the basic idea of process function. The time for one cycle through the program is called “scan time.” Typical values of scan time may be as low as 1 m/s. The input and output values are typically stored in memory unit per cycle or some of its multiple [53].

5.2.2.2 Processing unit

The central processing unit (CPU) is responsible for the management of all the operations of the sensor node, including the sampling of the available sensors, the processing of the data, and the correct forwarding of the information when needed. The CPU should be able to manage the sensor node activity while meeting the energy consumption, size, and cost constraints. There are a large number of microcontrollers (MCUs), microprocessors, and FPGAs suitable to be integrated in sensor nodes, with the MCUs as the preferred choice in terms of cost and hardware and software development. Modern embedded MCUs, ranging from ultra-low power 8-bit solutions, to high-performance 32-bit solutions, are equipped with a vast range of on-board peripherals including timers, analog-to-digital converters, and serial communication controllers, and they provide a complete solution for sensing nodes.

(1) PCI address spaces

The CPU and all the PCI devices need to access memory that is shared by them. Device drivers control the PCI devices and pass information between them by using this memory. Typically, this shared memory contains control and status registers for the device, which are used to control the device and to read its status. For example, the PCI SCSI device driver would read its status register to find out whether the device was ready to write a block of information, or it might write to the control register to start the device after it has been turned on.

The CPU’s system memory could be used for this shared memory but in this case, every time a PCI device accessed memory, the CPU would have to stall, waiting for it to finish. Access to memory is generally limited to one system component at a time. This would slow the system down. It does not allow the system’s peripheral devices to access main memory in an uncontrolled way. This would be very dangerous; a malfunctioning device could make the system very unstable.

Peripheral devices have their own memory spaces. The CPU can access these spaces, but access by the devices to the system’s memory is very strictly controlled, by using DMA (direct memory access) channels. ISA devices have access to two address spaces; ISA I/O (input/output) and ISA memory. With most advanced microprocessors, PCI must have three elements: PCI I/O, PCI memory, and PCI configuration space.

Some microprocessors, for example, the Alpha AXP processor, do not have natural access to address spaces other than the system address space. This processor uses support chipsets to access other address spaces such as the PCI configuration space by use of a sparse address-mapping scheme that steals part of the large virtual address space and maps it to the PCI address spaces.